View MB84VA2104_2387220.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds05-50108-1e fujitsu semiconductor data sheet mcp (multi-chip package) flash memory & sram cmos 16m ( 8) flash memory & 1m ( 8) static ram MB84VA2104 -10 /mb84va2105 -10 n features ? power supply voltage of 2.7 to 3.6 v ? high performance 100 ns maximum access time ? operating temperature C20 to +85 c flash memory ? minimum 100,000 write/erase cycles ? sector erase architecture one 16 k byte, two 8 k bytes, one 32 k byte, and thirty one 64 k bytes. any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture MB84VA2104: top sector mb84va2105: bottom sector ? embedded erase tm algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready-busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ?low v cc write inhibit 2.5 v ? erase suspend/resume suspends the erase operation to allow a read in another sector within the same device please refer to "mbm29lv160t/b" data sheet in detailed function sram ? power dissipation operating : 35 ma max. standby : 30 m a max. ? power down features using ce1 s and ce2s ? data retention supply voltage: 2.0 v to 3.6 v embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
2 MB84VA2104 -10 /mb84va2105 -10 n block diagram v ss v cc s 16 m bit reset flash memory we 1 m bit static ram ce f a 0 to a 20 oe ce1 s v ss v cc f a 0 to a 20 a 0 to a 16 dq 0 to dq 7 ry/by ce2s
3 MB84VA2104 -10 /mb84va2105 -10 n pin assignments (top view) abcdef gh 6ce1 sv ss dq 1 a 1 a 2 a 4 ce2s a 9 5a 10 dq 5 dq 2 a 0 a 3 a 7 ry/by a 15 4oe dq 7 dq 4 dq 0 a 6 a 19 reset a 16 3a 11 a 8 a 5 n.c. dq 3 n.c. a 13 a 20 2a 14 a 18 n.c. ce fn.c.v cc fdq 6 a 12 1we v cc sa 17 v ss n.c. n.c. n.c. n.c. table 1 pin configuration pin function input/ output a 0 to a 16 address inputs (common) i a 17 to a 20 address input (flash) i dq 0 to dq 7 data inputs/outputs (common) i/o ce f chip enable (flash) i ce1 s chip enable (sram) i ce2s chip enable (sram) i oe output enable (common) i we write enable (common) i ry/by ready/busy outputs (flash) o reset hardware reset pin/sector protection unlock (flash) i n.c. no internal connection v ss device ground (common) power v cc f device power supply (flash) power v cc s device power supply (sram) power
4 MB84VA2104 -10 /mb84va2105 -10 n product line up n bus operations legend: l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. notes: 1. other operations except for indicated this column are inhibited. 2. we can be v il if oe is v il , oe at v ih initiates the write operations. 3. do not apply ce f = v il , ce1 s = v il and ce2s = v ih at a time. flash memory sram ordering part no. v cc = 3.0 v MB84VA2104-10/mb84va2105-10 max. address access time (ns) 100 100 max. ce access time (ns) 100 100 max. oe access time (ns) 40 50 table 2 user bus operations operation (1), (3) ce fce1 sce2s oe we dq 0 to dq 7 reset full standby h hx xxhigh-z h xl output disable x x x h h high-z h read from flash (2) l hx lh d out h xl write to flash l hx hl d in h xl read from sram h l h l h d out h write to sram h l h x l d in h flash hardware reset x hx xxhigh-z l xl +0.6 v C0.3 v
5 MB84VA2104 -10 /mb84va2105 -10 n flexible sector-erase architecture on flash memory ? one 16 k byte, two 8 k bytes, one 32 k byte, and thirty one 64 k bytes. individual-sector, multiple-sector, or bulk-erase capability. . MB84VA2104 sector architecture sector size address range 64 kbytes 00000h to 0ffffh 64 kbytes 10000h to 1ffffh 64 kbytes 20000h to 2ffffh 64 kbytes 30000h to 3ffffh 64 kbytes 40000h to 4ffffh 64 kbytes 50000h to 5ffffh 64 kbytes 60000h to 6ffffh 64 kbytes 70000h to 7ffffh 64 kbytes 80000h to 8ffffh 64 kbytes 90000h to 9ffffh 64 kbytes a0000h to affffh 64 kbytes b0000h to bffffh 64 kbytes c0000h to cffffh 64 kbytes d0000h to dffffh 64 kbytes e0000h to effffh 64 kbytes f0000h to fffffh 64 kbytes 100000h to 10ffffh 64 kbytes 110000h to 11ffffh 64 kbytes 120000h to 12ffffh 64 kbytes 130000h to 13ffffh 64 kbytes 140000h to 14ffffh 64 kbytes 150000h to 15ffffh 64 kbytes 160000h to 16ffffh 64 kbytes 170000h to 17ffffh 64 kbytes 180000h to 18ffffh 64 kbytes 190000h to 19ffffh 64 kbytes 1a0000h to 1affffh 64 kbytes 1b0000h to 1bffffh 64 kbytes 1c0000h to 1cffffh 64 kbytes 1d0000h to 1dffffh 64 kbytes 1e0000h to 1effffh 32 kbytes 1f0000h to 1f7fffh 8 kbytes 1f8000h to 1f9fffh 8 kbytes 1fa000h to 1fbfffh 16 kbytes 1fc000h to 1fffffh mb84va2105 sector architecture sector size address range 16 kbytes 00000h to 03fffh 8 kbytes 04000h to 05fffh 8 kbytes 06000h to 07fffh 32 kbytes 08000h to 0ffffh 64 kbytes 10000h to 1ffffh 64 kbytes 20000h to 2ffffh 64 kbytes 30000h to 3ffffh 64 kbytes 40000h to 4ffffh 64 kbytes 50000h to 5ffffh 64 kbytes 60000h to 6ffffh 64 kbytes 70000h to 7ffffh 64 kbytes 80000h to 8ffffh 64 kbytes 90000h to 9ffffh 64 kbytes a0000h to affffh 64 kbytes b0000h to bffffh 64 kbytes c0000h to cffffh 64 kbytes d0000h to dffffh 64 kbytes e0000h to effffh 64 kbytes f0000h to fffffh 64 kbytes 100000h to 10ffffh 64 kbytes 110000h to 11ffffh 64 kbytes 120000h to 12ffffh 64 kbytes 130000h to 13ffffh 64 kbytes 140000h to 14ffffh 64 kbytes 150000h to 15ffffh 64 kbytes 160000h to 16ffffh 64 kbytes 170000h to 17ffffh 64 kbytes 180000h to 18ffffh 64 kbytes 190000h to 19ffffh 64 kbytes 1a0000h to 1affffh 64 kbytes 1b0000h to 1bffffh 64 kbytes 1c0000h to 1cffffh 64 kbytes 1d0000h to 1dffffh 64 kbytes 1e0000h to 1effffh 64 kbytes 1f0000h to 1fffffh
6 MB84VA2104 -10 /mb84va2105 -10 table 3 sector address tables (MB84VA2104) sector address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 address range sa0 0 0 0 0 0 x x x 00000h to 0ffffh sa1 0 0 0 0 1 x x x 10000h to 1ffffh sa2 0 0 0 1 0 x x x 20000h to 2ffffh sa3 0 0 0 1 1 x x x 30000h to 3ffffh sa4 0 0 1 0 0 x x x 40000h to 4ffffh sa5 0 0 1 0 1 x x x 50000h to 5ffffh sa6 0 0 1 1 0 x x x 60000h to 6ffffh sa7 0 0 1 1 1 x x x 70000h to 7ffffh sa8 0 1 0 0 0 x x x 80000h to 8ffffh sa9 0 1 0 0 1 x x x 90000h to 9ffffh sa10 0 1 0 1 0 x x x a0000h to affffh sa11 0 1 0 1 1 x x x b0000h to bffffh sa12 0 1 1 0 0 x x x c0000h to cffffh sa13 0 1 1 0 1 x x x d0000h to dffffh sa14 0 1 1 1 0 x x x e0000h to effffh sa15 0 1 1 1 1 x x x f0000h to fffffh sa16 1 0 0 0 0 x x x 100000h to 10ffffh sa17 1 0 0 0 1 x x x 110000h to 11ffffh sa18 1 0 0 1 0 x x x 120000h to 12ffffh sa19 1 0 0 1 1 x x x 130000h to 13ffffh sa20 1 0 1 0 0 x x x 140000h to 14ffffh sa21 1 0 1 0 1 x x x 150000h to 15ffffh sa22 1 0 1 1 0 x x x 160000h to 16ffffh sa23 1 0 1 1 1 x x x 170000h to 17ffffh sa24 1 1 0 0 0 x x x 180000h to 18ffffh sa25 1 1 0 0 1 x x x 190000h to 19ffffh sa26 1 1 0 1 0 x x x 1a0000h to 1affffh sa27 1 1 0 1 1 x x x 1b0000h to 1bffffh sa28 1 1 1 0 0 x x x 1c0000h to 1cffffh sa29 1 1 1 0 1 x x x 1d0000h to 1dffffh sa30 1 1 1 1 0 x x x 1e0000h to 1effffh sa31 111110xx 1f 0000h to 1f7fffh sa32 11111100 1f 8000h to 1f9fffh sa33 11111101 1fa000h to 1fbfffh sa34 1111111x 1fc000h to 1fffffh
7 MB84VA2104 -10 /mb84va2105 -10 table 4 sector address tables (mb84va2105) sector address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 address range sa0 0000000x 0 0000h to 03fffh sa1 00000010 0 4000h to 05fffh sa2 00000011 0 6000h to 07fffh sa3 0000010x 08 000h to 0ffffh sa4 0 0 0 0 1 x x x 10000h to 1ffffh sa5 0 0 0 1 0 x x x 20000h to 2ffffh sa6 0 0 0 1 1 x x x 30000h to 3ffffh sa7 0 0 1 0 0 x x x 40000h to 4ffffh sa8 0 0 1 0 1 x x x 50000h to 5ffffh sa9 0 0 1 1 0 x x x 60000h to 6ffffh sa10 0 0 1 1 1 x x x 70000h to 7ffffh sa11 0 1 0 0 0 x x x 80000h to 8ffffh sa12 0 1 0 0 1 x x x 90000h to 9ffffh sa13 0 1 0 1 0 x x x a0000h to affffh sa14 0 1 0 1 1 x x x b0000h to bffffh sa15 0 1 1 0 0 x x x c0000h to cffffh sa16 0 1 1 0 1 x x x d0000h to dffffh sa17 0 1 1 1 0 x x x e0000h to effffh sa18 0 1 1 1 1 x x x f0000h to fffffh sa19 1 0 0 0 0 x x x 100000h to 10ffffh sa20 1 0 0 0 1 x x x 110000h to 11ffffh sa21 1 0 0 1 0 x x x 120000h to 12ffffh sa22 1 0 0 1 1 x x x 130000h to 13ffffh sa23 1 0 1 0 0 x x x 140000h to 14ffffh sa24 1 0 1 0 1 x x x 150000h to 15ffffh sa25 1 0 1 1 0 x x x 160000h to 16ffffh sa26 1 0 1 1 1 x x x 170000h to 17ffffh sa27 1 1 0 0 0 x x x 180000h to 18ffffh sa28 1 1 0 0 1 x x x 190000h to 19ffffh sa29 1 1 0 1 0 x x x 1a0000h to 1affffh sa30 1 1 0 1 1 x x x 1b0000h to 1bffffh sa31 1 1 1 0 0 x x x 1c0000h to 1cffffh sa32 1 1 1 0 1 x x x 1d0000h to 1dffffh sa33 1 1 1 1 0 x x x 1e0000h to 1effffh sa34 1 1 1 1 1 x x x 1f0000h to 1fffffh
8 MB84VA2104 -10 /mb84va2105 -10 table 5. 1 flash memory autoselect code table 5. 2 expanded autoselect code table type a 12 a 6 a 1 a 0 code (hex) manufacturers code v il v il v il v il 04h device code MB84VA2104 v il v il v il v ih c4h mb84va2105 v il v il v il v ih 49h type code dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h 0 0 0 0 0 1 0 0 device code MB84VA2104 c4h11000100 mb84va2105 49h01001001
9 MB84VA2104 -10 /mb84va2105 -10 address bits a 11 to a 20 = x = h or l for all address commands except for program address (pa) and sector address (sa). bus operations are defined in table 2. both read/reset commands are functionally equivalent, resetting the device to the read mode. ra =address of the memory location to be read. pa =address of the memory location to be programmed. addresses are latched on the falling edge of the write pulse. sa =address of the sector to be erased. the combination of a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 will uniquely select any sector. rd =data read from location ra during read operation. pd =data to be programmed at location pa. spa =sector address to be protected. set sector address (sa) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd =sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. note: this command is valid while fast mode. table 6 flash memory command definitions command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1 xxxhf0h read/reset 3 555h aah 2aah 55h 555h f0h ra rd autoselect 3 555h aah 2aah 55h 555h 90h program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend erase can be suspended during sector erase with addr (h or l). data (b0h) sector erase resume erase can be resumed after suspend with addr (h or l). data (30h) set to fast mode 3 555h aah 2aah 55h 555h 20h fast program (note) 2 xxxh a0h pa pd reset from fast mode (note) 2xxxh90hxxxhf0h extended sector protect 4 xxxh 60h spa 60h spa 40h spa sd
10 MB84VA2104 -10 /mb84va2105 -10 n absolute maximum ratings storage temperature .................................................................................................. C55c to + 125c ambient temperature with power applied .................................................................. C25c to +85c voltage with respect to ground all pins (note) .......................................................... C0.3 v to v cc f +0.5 v C0.3 v to v cc s +0.5 v v cc f/v cc s supply (note) .............................................................................................. C0.3 v to +4.6 v note: minimum dc voltage on input or i/o pins are C0.5 v. during voltage transitions, inputs may negativeovershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins are v cc f +0.5 v or v cc s +0.5 v. during voltage transitions, outputs may positive overshoot to v cc +2.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum rating conditions. do not exceed these ratings. n recommended operating ranges commercial devices ambient temperature (t a ) .........................................................................C20c to +85c v cc f/v cc s supply voltages.........................................................................+2.7 v to +3.6 v operating ranges define those limits between which the functionality of the device is guaranteed. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand.
11 MB84VA2104 -10 /mb84va2105 -10 n dc characteristics parameter symbol parameter description test conditions min. typ. max. unit i li input leakage current C1.0 +1.0 m a i lo output leakage current C1.0 +1.0 m a i cc1 f flash v cc active current (read) v cc f = v cc max., ce f = v il oe = v ih t cycle = 10 mhz 30 ma t cycle = 5 mhz 15 i cc2 f flash v cc active current (program/erase) v cc f = v cc max., ce f = v il , oe = v ih 35ma i cc1 s sram v cc active current v cc s = v cc max., ce1 s = v il , ce2s = v ih tt cycle =10 mhz 40 ma t cycle = 1 mhz 12 ma i cc2 s sram v cc active current ce1 s = 0.2 v, ce2s = v cc s C 0.2 v, we = v cc s C 0.2 v t cycle = 10 mhz 35 ma t cycle = 1 mhz 8 ma i sb1 f flash v cc standby current v cc f = v cc max., ce f = v cc f 0.3 v reset = v cc f 0.3 v 5 m a i sb2 f flash v cc standby current (reset ) v cc f = v cc max., reset = v ss 0.3 v 5 m a i sb1 s sram v cc standby current ce1 s = v ih or ce2s = v il 2ma i sb2 s** sram v cc standby current ce1 s = v cc C 0.2 v or ce2s = 0.2 v v cc s = 3.0 v 10% t a = 25c 1 2 m a t a = C20 to +85c 35 m a v cc s = 3.3 v 0.3 v t a = 25c 2 3 m a t a = C20 to +85c 40 m a v cc s = 3.0 v t a = 25c 1 m a t a = C20 to +40c 3 m a t a = C20 to +85c 30 m a v il input low level C0.3 0.6 v v ih input high level 2.2 v cc +0.3* v v ol output low voltage level i ol = 2.1 ma, v cc f = v cc s = v cc min. 0.4v v oh output high voltage level i oh = C500 m a, v cc f = v cc s = v cc min. v cc C 0.5 v v lko flash low v cc lock-out voltage 2.32.5v * : v cc indicate lower of v cc f or v cc s ** :during standby mode with ce1 s = v ccs C 0.2 v, ce2s should be ce2s < 0.2v or ce2s > v ccs C 0.2v
12 MB84VA2104 -10 /mb84va2105 -10 n ac characteristics ?ce timing ? timing diagram for alternating sram to flash parameter symbols description test setup -10 unit jedec standard t ccr ce recover time min. 0 ns ce f t ccr t ccr ce1 s ce2s t ccr t ccr
13 MB84VA2104 -10 /mb84va2105 -10 ? read only operations characteristics (flash) note: test conditionsCoutput load: 1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level input: 1.5 v output: 1.5 v parameter symbols description test setup -10 (note) unit jedec standard min. max. t avav t rc read cycle time 100 ns t avqv t acc address to output delay ce f = v il oe = v il 100ns t elqv t ce f chip enable to output delay oe = v il 100ns t glqv t oe output enable to output delay 40 ns t ehqz t df chip enable to output high-z 30 ns t ghqz t df output enable to output high-z 30 ns t axqx t oh output hold time from addresses, ce f or oe , whichever occurs first 0ns t ready reset pin low to read mode 20 s
14 MB84VA2104 -10 /mb84va2105 -10 ? read cycle (flash) we oe ce f t ce t oe dq addresses stable high-z output valid high-z t oeh t acc t rc reset t acc t oh dq t rc addresses stable high-z output valid t rh t df addresses addresses
15 MB84VA2104 -10 /mb84va2105 -10 ? erase/program operations (flash) note : 1. this does not include the preprogramming time. 2. this timing is for sector protection operation. parameter symbols description -10 unit jedec standard min. typ. max. t avav t wc write cycle time 100 ns t avwl t as address setup time (we to addr.) 0 ns t avel t as address setup time (ce f to addr.) 0 ns t wlax t ah address hold time (we to addr.) 50 ns t elax t ah address hold time (ce f to addr.) 50 ns t dvwh t ds data setup time 50 ns t whdx t dh data hold time 0 ns t oes output enable setup time 0 ns t oeh output enable hold time read 0 ns toggle and data polling 10 ns t ghel t ghel read recover time before write (oe to ce f) 0 ns t ghwl t ghwl read recover time before write (oe to we )0ns t wlel t ws we setup time (ce f to we )0ns t elwl t cs cef setup time (we to ce f) 0 ns t ehwh t wh we hold time (ce f to we )0ns t wheh t ch cef hold time (we to ce f) 0 ns t wlwh t wp write pulse width 50 ns t eleh t cp ce f pulse width 50 ns t whwl t wph write pulse width high 30 ns t ehel t cph cef pulse width high 30 ns t whwh1 t whwh1 byte programming operation 8 s t whwh2 t whwh2 sector erase operation (note 1) 1 sec 15sec t vcs v cc f setup time 50 s t vlht voltage transition time (note 2) 4 s t vidr rise time to v id (note 2) 500 ns t rb recover time from ry/by 0ns t rp reset pulse width 500 ns t rh reset hold time before read 200 ns t eoe delay time from embedded output enable 100 ns t busy program/erase valid to ry/by delay 90 ns
16 MB84VA2104 -10 /mb84va2105 -10 ? write cycle (we control) (flash) t ch t wp t whwh1 t wc t ah ce f oe t rc dq t as t f oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t co t ds d out addresses
17 MB84VA2104 -10 /mb84va2105 -10 ? write cycle (ce f control) (flash) notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. t cp t ds t whwh1 t wc t ah we oe dq t as t cph t dh dq 7 a0h d out ce f 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd addresses
18 MB84VA2104 -10 /mb84va2105 -10 ? ac waveforms chip/sector erase operations (flash) addresses v cc ce f oe dq we 555h 2aah 555h 555h 2aah sa *1 t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc t wp aah 55h 80h aah 55h 10h/ 30h for sector erase note: 1. sa is the sector address for sector erase. addresses = 555h for chip erase. 30h
19 MB84VA2104 -10 /mb84va2105 -10 ? ac waveforms for data polling during embedded algorithm operations (flash) ? ac waveforms for taggle bit during embedded algorithm operations (flash) *dq 7 = valid data (the device has completed the embedded operation.) t oeh t f oe t whwh1 or 2 ce f oe we dq 7 t o d t ch t co dq 7 = valid data dq 7 * dq dq 0 to dq 6 = invalid t eoe dq 0 to dq 6 valid data high-z high-z (dq 0 to dq 6 ) data in data in * *dq 6 = stops toggling. (the device has completed the embedded operation.) ce f we oe data in dq 6 = toggle dq 6 = stop toggling dq 0 to dq 7 data valid t eoe dq 6 = t oeh t oes dq 6 toggle
20 MB84VA2104 -10 /mb84va2105 -10 ?ry/by timing diagram during write/erase operations (flash) ? reset , ry/by timing diagram (flash) ? temporary sector unprotection (flash) the rising edge of the last we signal ce f ry/by we t busy entire programming or erase operations t rp reset t ready ry/by we t rb 3 v reset v cc ce we ry/by t vlht program or erase command sequence 3 v t vlht t vcs t vidr v id t vlht unprotection period
21 MB84VA2104 -10 /mb84va2105 -10 ? extended sector protection (flash) spax : sector address to be protected spay : next sector address to be protected time-out : time-out window = 150 m s (min) spay reset a 6 oe we ce data a 1 v cc a 0 add spax spax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe
22 MB84VA2104 -10 /mb84va2105 -10 ? read cycle (sram) ? read cycle (note 1) (sram) note: 1. we remains high for the read cycle. parameter symbol parameter description min. max. unit t rc read cycle time 100 ns t aa address access time 100 ns t co1 chip enable (ce1 s) access time 100 ns t co2 chip enable (ce2s) access time 100 ns t oe output enable access time 50 ns t coe chip enable (ce1 s low and ce2s high) to output active 5 ns t oee output enable low to output active 0 ns t od chip enable (ce1 s high or ce2s low) to output high-z 40 ns t odo output enable high to output high-z 40 ns t oh output data hold time 10 ns t rc t aa t oh t co1 t od t odo t oee t coe valid data out addresses ce1 s oe dq ce2s t coe t oe t co2 t od
23 MB84VA2104 -10 /mb84va2105 -10 ? write cycle (sram) ? write cycle (note 4) (we control) (sram) parameter symbol parameter description min. max. unit t wc write cycle time 100 ns t wp write pulse width 60 ns t cw chip enable to end of write 80 ns t as address setup time 0 ns t wr write recovery time 0 ns t odw we low to output high-z 40 ns t oew we high to output active 0 ns t ds data setup time 60 ns t dh data hold time 0 ns t wc t as t wp t wr t cw t odw t oew t ds t dh valid data in addresses we ce1 s d out d in ce2s t cw notes: 2. if ce1 s goes low (or ce2s goes high) coincident with or after we goes low, the output will remain at high impedance. 3. if ce1 s goes high (or ce2s goes low) coincident with or before we goes high, the output will remain at high impedance. 4. if oe is high during the write cycle, the outputs will remain at high impedance. 5. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. note 2 note 5 note 3 note 5
24 MB84VA2104 -10 /mb84va2105 -10 ? write cycle (note 4) (ce 1s control) (sram) t wc t as t wp t wr t cw t odw t coe t ds t dh valid data in addresses we ce1 s d out d in ce2s t cw notes: 2. if ce1 s goes low (or ce2s goes high) coincident with or after we goes low, the output will remain at high impedance. 3. if ce1 s goes high (or ce2s goes low) coincident with or before we goes high, the output will remain at high impedance. 4. if oe is high during the write cycle, the outputs will remain at high impedance. 5. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. note 5 note 5
25 MB84VA2104 -10 /mb84va2105 -10 ? write cycle (note 4) (ce2s control) (sram) t wc t as t wp t wr t cw t odw t coe t ds t dh valid data in addresses we ce1 s d out d in ce2s notes: 2. if ce1 s goes low (or ce2s goes high) coincident with or after we goes low, the output will remain at high impedance. 3. if ce1 s goes high (or ce2s goes low) coincident with or before we goes high, the output will remain at high impedance. 4. if oe is high during the write cycle, the outputs will remain at high impedance. 5. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. note 5 note 5 t cw
26 MB84VA2104 -10 /mb84va2105 -10 n erase and programming performance (flash) n data retention characteristics (sram) * : 5 m a (max.) at t a = C20c to +40c ?ce1 s controlled data retention mode (note 1) parameter limits unit comment min. typ. max. sector erase time 1 15 sec excludes programming time prior to erasure byte programming time 8 3,600 m s excludes system-level overhead chip programming time 16.8 100 sec excludes system-level overhead erase/program cycle 100,000 cycles parameter symbol parameter description min. typ. max. unit v dh data retention supply voltage 2.0 3.6 v i dds2 standby current v dh = 3.0 v 30* m a v dh = 3.6 v 40 m a t cdr chip deselect to data retention mode time 0 ns t r recovery time 5 ms v cc s 2.7 v v ih gnd data retention mode see note 2 t cdr ce1 s v ccs C0.2 v see note 2 t r
27 mb84 v a2104 -10 /mb84 v a2105 -10 ? ce2s cont r olled data retention mode (note 3) notes: 1 . in ce1 s controlled data retention mod e , input l e v el of ce2s should be fi x ed vccs to vccs-0.2v or vss to 0.2v du r i ng data retention mod e . other input and input/output pins can be used bet w een -0.3v to vccs+0.3 v . 2.when ce1 s is ope r ating at the v ih min. l e v el (2.2 v), the stand b y current is gi v en b y i sb1 s du r ing the t r ansition of v cc s from 3.6 to 2.2 v . 3 . in ce2s controlled data retention mod e , input and input/output pins can be used bet w een bet w een -0.3v to vccs+0.3 v . n pin ca p a ci t ance note : t est conditions t a = 25 c , f = 1.0 mhz n hand ling of p a ck a ge please handle this pa c kage carefully since the sides of pa c kages are r ight angl e . n c a ution 1 . )the high v oltage (vid) can not apply to address pins and control pins e xcept reset . there f or e , it can not use autoselect and sector protect function b y applying the high v oltage (vid) to specific pin s . 2 . ) f or the sector protection, since the high v oltage (vid) can be applied to the reset , it can be protected the sector useing "extended sector protect" command. parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 t.b.d t.b.d pf c out output capacitance v out = 0 t.b.d t.b.d pf c in2 control pin capacitance v in = 0 t.b.d t.b.d pf v cc s 2.7 v gnd data retention mode v ih v il ce2s t cdr t r 0.2 v
28 MB84VA2104 -10 /mb84va2105 -10 n pac k ag e n package dimensions 48-pin plastic fbga (bga-48p-m10) c 1998 fujitsu limited mcm-m002-3-2 10.00?.15 0.30?.10 (.012?004) 1.40?.20 (.055?008) 5.00?.15 (.197?006) (.394?006) 1.00?.15 (.039?006) 7.00?.15(.276?006) 0.15(.006) 14.00?.15(.551?006) index 1st pin 0.40?.10 (.016?004) index dimension in mm (inches). 48-pin plastic bga (bga-48p-m10) note: the actual shape of coners may differ from the dimension.
29 MB84VA2104 -10 /mb84va2105 -10 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: (044) 754-3763 fax: (044) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9805 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MB84VA2104

	To Download MB84VA2104 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .